1. Field of the Invention
The present invention relates to a semiconductor device, a battery protection circuit and a battery pack, and in particular the semiconductor device relates to a bidirectional power Metal-Oxide-Semiconductor-Field-Effect Transistor (hereinafter referred to as MOSFET).
2. Related Art
A battery pack is frequently used as a power supply for mobile devices such as mobile phones and the like and for information equipment such as personal computers and the like. FIG. 14 is a block diagram showing the configuration of a battery pack 40. In the drawings, a charger 50 is shown charging a battery 41 of the battery pack 40. In normal use, a load such as circuitry of a mobile device is connected to the battery pack 40 instead of the charger 50.
When the battery pack 40 is used as the power supply for a mobile device and the like, electric power is supplied to the mobile device (which is not illustrated) through input-output terminals Pack+ and Pack− of the battery pack 40. On the other hand, a positive electrode (the high potential side) of the charger 50 is connected to the plus side input-output terminal Pack+ of the battery pack 40 so that current flows from the charger 50 into a positive electrode (the plus side) of the battery 41 when the battery 41 are charged. The plus side input-output terminal Pack+ is connected to the positive electrode of the battery 41.
The battery pack 40 includes the battery 41 and a battery protection Integrated Circuit (hereinafter referred to as IC) 30. The battery protection IC 30 consists of a bidirectional lateral power MOSFET 31 functioning as a battery protection switch and a control circuit section 32 controlling the bidirectional lateral power MOSFET 31. The bidirectional lateral power MOSFET 31 consists of two nMOSFETs 33 and 34 and two diodes 35 and 36.
The source and the drain of the nMOSFET 33 disposed on the right side in FIG. 14 are respectively connected to the anode and the cathode of the diode 35. The source and the drain of the nMOSFET 34 disposed on the left side in FIG. 14 are respectively connected to the anode and the cathode of the diode 36. In this manner an FET and a diode are connected in parallel and polarity is reversed to a normal connection, and the connection is referred to as an inverse-parallel connection.
In addition, in the bidirectional lateral power MOSFET 31, when the nMOSFET 33 disposed on the right side is distinguished from the nMOSFET 34 disposed on the left side, the nMOSFET 33 and the nMOSFET 34 are described respectively as the right nMOSFET 33 and the left nMOSFET 34. The diode 35 and the diode 36 are described respectively as the right diode 35 and the left diode 36 as well as the right nMOSFET 33 and the left nMOSFET 34. The drain of the right nMOSFET 33 is connected to the drain of the left nMOSFET 34. In this manner it is referred to as anti-series connection, in which the two FETs are connected in series and are connected so that polarity is reversed to a normal connection.
A source terminal S1 (hereinafter referred to as the first source terminal S1) of the right nMOSFET 33 is connected to the minus side input-output terminal Pack−. A source terminal S2 (hereinafter referred to as the second source terminal S2) of the left nMOSFET 34 is connected to negative pole (the minus side) of the battery 41. A gate terminal G1 (hereinafter referred to as the first gate terminal G1) of the right nMOSFET 33 and the gate terminal G2 (hereinafter referred to as the second gate terminal G2) of the left nMOSFET 34 are connected to the control circuit section 32. The right nMOSFET 33 and the left nMOSFET 34 are controlled by the control circuit section 32.
The positive pole (the plus side) of the battery 41 is connected to the plus side input-output terminal Pack+. The load (such as a mobile-phone) and the charger 50 for charging the battery are connected to these input-output terminals Pack+ and Pack−. The control circuit section 32 is connected to the plus side input-output terminal Pack+ of the battery pack 40 through a resistor which is not illustrated. In addition, the control circuit section 32 is connected to the minus side input-output terminal Pack− through a resistor (which is not illustrated). A bidirectional Trench Lateral Power MOSFET (hereinafter referred to as TLPM) can be applied as the bidirectional lateral power MOSFET 31. The structure of the bidirectional TLPM will now be explained.
FIG. 15 is a cross sectional view showing a principle part of a bidirectional TLPM. FIG. 16 is a circuit diagram showing an equivalent circuit of the bidirectional TLPM shown in FIG. 15. FIG. 17 is a plane view showing a principle part of a conventional bidirectional TLPM. FIG. 15 is a cross sectional view along the line segment X-X of FIG. 17.
As shown in FIG. 16, a bidirectional TLPM 20 includes two input-output terminals (the first source terminal S1 and the second source terminal S2) and two gate terminals (the first gate terminal G1 and the second gate terminal G2). When both the first nMOSFET 21 and the second nMOSFET 22 are in an on state, current flows to the bidirectional TLPM 20 even if voltage is applied to either the input-output terminal S1 or S2. When both the first nMOSFET 21 and the second nMOSFET 22 are in an off state, current does not flow to the bidirectional TLPM 20 even if voltage is applied to either the input-output terminal S1 or S2.
As shown in FIGS. 15 and 16, the bidirectional TLPM 20 is a four-terminal element having the first and the second source terminals S1 and S2 and the first and the second gate terminals G1 and G2. The two MOSFETs 21 and 22 have a common drain region 4. A method for manufacturing of the bidirectional TLPM 20 will now be explained with reference to FIG. 15.
At first an n well region 2 is formed in a surface layer of a p substrate 1. Subsequently, by ion implantation and thermal diffusion, a p base region is formed in a surface layer of the n well region 2. Subsequently a trench 3 reaching the n well region 2 through the p base region from a surface of the p base region is formed. The p base region is divided by the trench 3, and thereby the p base region becomes a first p base region 10 and a second p base region 11. The first p base region 10 and the second p base region 11 are formed respectively by a surface layer of a first n silicon pillar 8 of a trench remaining portion and a surface layer of a second n silicon pillar 9 of the trench remaining portion.
Subsequently, the common n drain region 4 is formed in the bottom of the trench 3 by ion implantation and thermal diffusion. Subsequently, a gate insulation film 5 is formed by thermal oxidation, and a first gate electrode 6 and a second gate electrode 7 are formed on respective portions of the gate insulation film 5 at the same time. Subsequently, by ion implantation and thermal diffusion, a first n source region 12 and a second n source region 14 are formed respectively in a surface layer of a first p base region 10 and a surface layer of a second p base region 11, and are formed in contact with the sidewall of trench 3.
In addition, a first base contact region 13 and a second base contact region 15 are formed respectively in a surface layer of the first p base region 10 and a surface layer of the second p base region 11 at the same time. Subsequently the trench 3 is buried with an interlayer insulation film 18. Subsequently a first source electrode 16 in contact with both the first n source region 12 and the first base contact region 13 and a second source electrode 17 in contact with both the second n source region 14 and a second base contact region 15 are formed at the same time.
The first source electrode 16 and the second source electrode 17 are connected respectively to the first source terminal S1 and the second source terminal S2. In addition, the first gate electrode 6 and the second gate electrode 7 are connected respectively to the first gate terminal G1 and the second gate terminal G2. In the bidirectional TLPM 20 fabricated as described above, a first nMOSFET 21 consists of a first n source region 12, the first p base region 10 and the common n drain region 4.
A second nMOSFET 22 consists of the n source region 14, the second p base region 11 and the common n drain region 4. In addition, a first diode 23 connected in inverse parallel to the first nMOSFET 21 consists of the first base contact region 13, the first p base region 10 and the common n drain region 4. A second diode 24 connected in inverse parallel to the second nMOSFET 22 consists of the second base contact region 15, the second p base region 11 and the common n drain region 4.
As shown in FIG. 17, the first n source region 12 is on the inside of the trench 3, which is configured as a closed curve. The first gate electrode 6 (which is not illustrated in FIG. 17) is disposed on an inner sidewall of the trench 3, and the second gate electrode 7 (which is not illustrated in FIG. 17) is disposed on an outer sidewall of the trench 3. The second n source region 14 is also located by the outer sidewall. In this structure, since an electric field is concentrated in the section B when the potential of the first n source region 12 is higher than that of the second n source region 14, the off breakdown voltage of the second nMOSFET 22 is determined in the section B due to an avalanche breakdown being caused.
On the other hand, since the electric field is concentrated in the section A when potential of the second n source region 14 is higher than that of the first n source region 12, the off breakdown voltage of the first nMOSFET 21 is determined in the section A due to an avalanche breakdown being caused. In other words, since there are sections (the section A and the section B) where the electric field concentrates in the first n source region 12 and the second n source region 14, the off breakdown voltage is determined thereby.
Japanese Patent Laid-Open number 59-5673 (Patent literature 1) discloses a lateral bidirectional FET in which a source region and a channel area are respectively separated to two areas by a notch extending to a drift region and a gate means is provided in the notch. Japanese Patent Laid-Open number 59-5674 (Patent literature 2) discloses a planar-type bidirectional FET in which a gate is divided. Japanese Patent Laid-Open number 2004-274039 (Patent literature 3) discloses a method in which an on-state voltage can be reduced in a high breakdown voltage in a trench-type bidirectional TLPM. Japanese Patent Laid-Open number 11-224950 (Patent literature 4) discloses a planar-type and a lateral-type bidirectional FET.
The operation of the configuration shown in FIG. 14 will now be explained for the case where the battery 41 is charged from the charger 50. When the charger 50 is connected to the battery pack 40 in the proper polarity, the voltage of the charger 50 is applied so that the plus side input-output terminal Pack+ of the battery pack 40 becomes a high potential and the minus side input-output terminal Pack− becomes a low potential. If the battery system has a rated output voltage of 20 V, the first source terminal S1 of the bidirectional lateral power MOSFET 31 is at 0 V, and the voltage of (20 V−4.2 V=15.8 V) that subtracted the voltage of the battery 41 (for example, 4.2 V that is taken as an overcharge) from the voltage of the charger 50 is applied to the second source terminal S2 at the maximum.
On the other hand, it is necessary for the battery pack not to be damaged when the polarity of the charger 50 is connected in reverse by mistake. In that case, the maximum voltage applied to bidirectional lateral power MOSFET 31 is 20 V+4.2 V=24.2 V since the voltage of battery 41 is added to the voltage of the charger 50. The voltage of 24.2 V is applied to the bidirectional lateral power MOSFET 31 so that the first source terminal S1 becomes plus and the second source terminal S2 becomes minus.
When the charger 50 is connected in proper polarity, the left nMOSFET 34 does not share the voltage since the left diode 36 is forward biased. Thus, a voltage of 15.8 V is applied to the right nMOSFET 33. On the other hand, because the right diode 35 is forward biased when the charger 50 is connected in reverse polarity, the right nMOSFET 33 does not share the voltage. Thus, a voltage of 24.2 V is applied to the left nMOSFET 34.
In other words, the breakdown voltages of the right nMOSFET 33 and the left nMOSFET 34 do not have to be always the same. The battery pack 40 can be used even if the breakdown voltage when the second source terminal S2 becomes high potential and the first source terminal S1 becomes low potential (namely the breakdown voltage of the right nMOSFET 33) is lowered, and even if the breakdown voltage when the second source terminal S2 becomes low potential and the first source terminal S1 becomes high potential (namely the breakdown voltage of the left nMOSFET 34) is made high.
In addition, the operation will be explained in the case where the charger 50 cannot be connected to the battery pack 40 in reverse polarity. When the second source terminal S2 becomes high potential and the first source terminal S1 becomes low potential, the first source terminal S1 is at 0 V, and the voltage of 15.8 V is applied to the second source terminal S2 at the maximum. In other words, the voltage of 15.8 V is applied to the right nMOSFET 33 at the maximum.
When the first source terminal S1 becomes high potential and the second source terminal S2 becomes low potential, the second source terminal S2 is at 0 V, and the voltage of 4.2 V is applied to the first source terminal S1 at the maximum. In other words, the voltage of 4.2 V is applied to the left nMOSFET 34 at the maximum. Thus, even if the breakdown voltage of the right nMOSFET is made high and the breakdown voltage of the left nMOSFET 34 is lowered, the battery pack 40 can be used.
However, in the conventional bidirectional TLPM, the breakdown voltages of two MOSFETs composing the bidirectional FET are designed equal. Therefore the width of the trench is enlarged more than required, and the curvature (reciprocal of radius of curvature) of the circular portions such section A or B as shown FIG. 17 of the plane pattern of the trench shrinks. Since the current path becomes long when the width of trench becomes wide, and in addition, the channel density is reduced due to radius of curvature, which grows big when the curvature of the circular portion in the plane pattern of the trench becomes small, there is the problem that on-resistance becomes high.
On the contrary, in the case where the breakdown voltages of two MOSFETs are put together in the breakdown voltage of a low one, the breakdown voltage is insufficient when the charger 50 is connected to the battery pack 40 in reverse polarity. Therefore the bidirectional lateral power MOSFET 31 enters into the avalanche mode and there is a danger that the battery pack 40 might not operate safely. In addition, it is not described in the above Patent literatures 1 through 4 that a trade off of on-resistance and the breakdown voltage is improved by making the breakdown voltages of a bidirectional element asymmetry.